Congratulations to Brian Dandurand who has received notification that his Individual Fellowship proposal entitled “Scaling Parallelism and Convexity Hurdles in Bi-Level Machine Learning” has been proposed for funding.
More details will follow in due time.
Deadline: 26/02/2024
Lecturer/Senior Lecturer in Distributed Computing
Lecturer/Senior Lecturer in Emerging Computing Technologies
Lecturer/Senior Lecturer in High Performance Computing
Lecturer/Senior Lecturer in Programming Languages & Compilers
We are recruiting a post-doctoral researcher or research assistant with expertise in parallel computing and GPU programming to work on the RAPID project, looking at real-time analytics in manufacturing.
Closing date is 6 December 2023.
Advert: https://hrwebapp.qub.ac.uk/tlive_webrecruitment/wrd/run/ETREC107GF.open?VACANCY_ID=697817LSP2&WVID=6273090Lgx&LANG=USA
Thesis on QUB Pure Portal
Thesis in PDF Format
Author: Dimitrios Christofidellis
Research has been conducted for numerous centuries but recent advances in technology have facilitated and accelerated the process keeping the research budget and the required effort at manageable levels. Scientific and technical corpora, such as papers and patents, are great written sources of already existing research knowledge and information. The abundance of such documents, in addition to their exponential growth, set them as a unique source of knowledge offering a great opportunity to push the research boundaries even further. Yet, this information’s volume and growth rate are so large that it is unmanageable for researchers to study all of it. Realizing the potential of incorporating this knowledge efficiently into the discovery process and that the recent advances in the NLP domain provide us with a powerful methodological base, our work aims to establish methods that can speed up parts of the discovery process relying on scientific and technical corpora. We focus on but do not limit our work on patent corpora as methods to leverage such documents in discovery pipelines are limited so far. Our contributions focus on three specific cases: the domain definition of a given corpus in the form of a metagraph; the domain definition of a given corpus in the form of keywords, focusing on the patent classification case; and the semi-automated reporting of a discovery artifact in the form of a patent. In all three cases, we rely on transformer-based Language Models and adhere to domain adaptive techniques to achieve our goals by providing efficient methods in terms of both performance and needed training/inference requirements. Concluding our work, we discuss the importance of our contributions. We demonstrate how our proposed methods can be incorporated into discovery pipelines, combined, and complement existing methods. We conclude with a discussion of promising future directions derived from our work.
We have 3 recruitment opportunities in a Marie Curie Doctoral Training Network on data analytics. These are PhD opportunities with a research assistant contract:
(1) Application-Aware Relaxed Synchronisation for Distributed Graph Processing, (offered)
(2) Interactive and intelligent exploration of big complex data, (offered) and
(3) Efficient and Responsible Analytics for Urban Mobility and Allied Applications (offered).
Application Deadlines
7 May 2023
RELAX Doctoral Network
The RELAX Doctoral Network brings together 5 cross-disciplinary research groups working across data science, data management, distributed computing and computing systems to pursue a fundamentally new approach to this problem by leveraging the semantics or correctness conditions of applications, with the goal of enhancing scalability, response times, and availability. The Doctoral Network provides a bespoke technical and non-technical training programme and fosters cross-disciplinary and third-party collaborations.
Funding Information
This project is funded by the Engineering and Physical Sciences Research Council grant number EP/X029174/1.
To be eligible for consideration for a RELAX Doctoral Candidate position (covering tuition fees and a basic salary with pension of approx. £33,001 per annum), a candidate must satisfy all the eligibility criteria based on transnational mobility and academic qualifications. The Studentship is open to all nationalities.
Applicants MUST be doctoral candidates, i.e. not already in possession of a doctoral degree at the date of the recruitment (understood as the recruitment call deadline) and undertake transnational mobility (see mobility rule below). Researchers who have successfully defended their doctoral thesis but who have not yet formally been awarded the doctoral degree will not be considered eligible.
Mobility Rule
Researchers must not have resided or carried out their main activity (work, studies, etc.) in the United Kingdom for more than 12 months in the 36 months immediately before their date of recruitment. Compulsory national service, short stays such as holidays, and time spent as part of a procedure for obtaining refugee status under the Geneva Convention are not taken into account.
Academic Requirements
The minimum academic requirement for admission is normally an Upper Second Class Honours degree from a UK or ROI Higher Education provider in a relevant discipline, or an equivalent qualification acceptable to the University.
More Information
Applicants may additionally consider applying to positions with the partner universities of the network: http://www.relax-dn.eu/
Date: 6th March 2023
Location: CSB Training Room 02.017
Parallel computing is a key technology supporting high-performance computing (HPC) and data analytics. The goal of this module is to provide an overview of parallel computing and introduce attendees to prevailing programming models. The expected outcome of this module is that participants will have an understanding of the different languages and approaches used in this domain and that they will be able to construct simple parallel programs using the discussed languages.
Theoretical lectures and practical training will be dispensed by Hans Vandierendonck, Romain Garnier, Syed Ibtisam Tauhidi, Amir Sabbagh Molahosseini, and Zohreh Moradinia. A general overview of High performance computing will be presented in the morning by Romain Garnier and Amir Sabbagh Molahosseini following by lab classes using practical examples with OpenMP. In the afternoon Syed Ibtisam Tauhidi and Zohreh Moradinia will present how to efficiently handle data analytics with Hadoop and Spark.
The design of efficient and scalable scientific simulation software is reaching a critical point whereby continued advances are increasingly harder, more labour-intensive, and thus more expensive to achieve. This challenge emanates from the constantly evolving design of large-scale high-performance computing systems. World-leading (pre-)exascale systems, as well as their successors, are characterised by multi-million-scale parallel computing activities and a highly heterogeneous mix of processor types such as high-end many-core processors, Graphics Processing Units (GPU), machine learning accelerators, and various accelerators for compression, encryption and in-network processing. To make efficient use of these systems, scientific simulation software must be decomposed in various independent components and make simultaneous use of the variety of heterogeneous compute units.
Developing efficient, scalable scientific simulation software for these systems becomes increasingly harder as the limits of parallelism available in the simulation codes is approached. Moreover, the limit of parallelism cannot be reached in practice due to heterogeneity, system imbalances and synchronisation overheads. Scientific simulation software often persists over several decades. The software is optimised and re-optimised repeatedly as the design and scale of the target hardware evolves at a much faster pace, as impactful changes in the hardware may occur every few years. One may thus find that the guiding principles that underpin such software are outdated.
The ASCCED project will fundamentally change the status quo in the design of scientific simulation software by simplifying the design to reduce software development and maintenance effort, to facilitate performance optimisation, and to make software more robust to future evolution of computing hardware. The key distinguishing factor of our approach is to structure scientific simulation software as a collection of loosely coupled parallel activities. We will explore the opportunities and challenges of applying techniques previously developed for Parallel Discrete Event Simulation (PDES) to orchestrate these loosely coupled parallel activities. This radically novel approach will enable runtime system software to extract unprecedented scales of parallelism and to minimise performance inefficiencies due to synchronisation. Additionally, based on a speculative execution mechanism, it will uncover parallelism that has not been feasible to extract before.
The computational model proposed by ASCCED will, if successful, initiate a new direction of research within programming models for high-performance computing that may dramatically impact not only the performance of scientific simulation software, but can also reduce the engineering effort required to produce efficient scientific simulation software. It will have a profound impact on the sciences that are highly dependent on leadership computing capabilities, such as climate modeling and cancer research.
This is a follow-up work on TOD, which selects one of multiple deep neural networks (DNNs) to perform real-time video analytics (object detection) on low-end devices, e.g., on the camera itself. TOD uses the median object size to determine which one out of 4 YOLO DNNs will meet the real-time requirement best, with respect to object size and speed of the objects. TOD requires specific knowledge of the device to select appropriate thresholds on the median object sizes, and needs to be retuned for each computing device.
ROMA removes the limitation that TOD imposes by performing a more detailed analysis of the image content. In particular, ROMA separately estimates the impact of the selected DNN on object size and on object speed. Its formulation is sufficiently flexible to adapt to changes in the computational power of the device such that it does not need to be retrained when migrating across hardware. Moreover, this way, ROMA can adapt to runtime changes in computational power, which may arise from power management features on the device, or from other workloads which share the device. ROMA does however have hyper-parameters that are dependent on the YOLO DNNs.
ROMA will be presented at the 2023 IEEE/CVF Winter Conference on Applications of Computer Vision (WACV).
You can read the post-print on arXiv.
Real-time video analytics on the edge is challenging as the computationally constrained resources typically cannot analyse video streams at full fidelity and frame rate, which results in loss of accuracy. We propose a Transprecise Object Detector (TOD) which maximises the real-time object detection accuracy on an edge device by selecting an appropriate Deep Neural Network (DNN) on the fly with negligible computational overhead.
TOD makes two key contributions over the state of the art: (1) TOD leverages characteristics of the video stream such as object size and speed of movement to identify networks with high prediction accuracy for the current frames; (2) it selects the best-performing network based on projected accuracy and computational demand using an effective and low-overhead decision mechanism.
Experimental evaluation on a Jetson Nano demonstrates that TOD improves the average object detection precision by 34.7 % over the YOLOv4-tiny-288 model on average over the MOT17Det dataset. In the MOT17-05 test dataset, TOD utilises only 45.1 % of GPU resource and 62.7 % of the GPU board power without losing accuracy, compared to YOLOv4-416 model. We expect that TOD will maximise the application of edge devices to real-time object detection, since TOD maximises real-time object detection accuracy given edge devices according to dynamic input features without increasing inference latency in practice.
TOD was presented at the 5th International Conference on Fog and Edge Computing (ICFEC). Read the paper on arXiv.
This projects aims to develop algorithms for real-time processing for analytics in digital factories. A particular use case is the design of hardware circuits, where silicon can easily be damaged during manufacturing. The production defects that arise negatively affect yield and/or quality of the devices. Uncovering these defects, and how they may be mitigated through tunable process parameters, is a demanding process, especially considering the high production rate and voluminous metrics that are collected.
The project considers the design of sketching algorithms, transprecise computing and their efficient implementation on modern high-throughput hardware such as graphics processing units.
RAPID is sponsored by EPSRC.
Project members: